A Phase Locked Loop (PLL) is a well-known circuit for deriving a steady (sometimes changeable or tunable) high frequency output signal. PLL are widely used in communication circuits, such as for generating carrier and local oscillator frequency signals for the modulation and demodulation of radio communication signals. PLLs compare a divided Radio Frequency (RF) signal with a reference clock to achieve phase lock, thus stabilizing the frequency of the undivided RF output. FIG. 7 depicts a functional block diagram of a conventional analog PLL. A Phase Frequency Detector (PFD) 12 compares the phases of a reference clock from a precision source 14, such as a crystal oscillator, to a feedback signal from a divider 16. The divider 16 divides down an RE output signal to the PLL operating frequency. The PFD 12 converts the phase difference between the reference clock and the divided RF signal into a control voltage level output. The PFD 12 output is low-pass filtered by a filter 18, and the control voltage is input to a Voltage Controlled Oscillator (VCO) 19 that changes the frequency of an RF output signal in response to the control voltage level.
Recently, digital PLL (DPLL) architectures have evolved, in which the phase difference is measured in a quantized fashion and converted into a digital control code for a Digitally Controlled Oscillator (DCO). In phase-domain PLLs, substantial analog circuitry is required to achieve sufficiently fine phase resolution to meet the phase noise requirements. One such circuit is a time-to-digital converter (TDC). A TDC is a device for converting a signal comprising pulses (or state transition edges) into a digital representation of their time indices. That is, a TDC outputs the time of arrival for each pulse, or edge, of a periodic signal.
Prior art phase-domain DPLLs have numerous deficiencies. Accurate representation of the control parameter in the phase domain requires infinite dynamic range (since the phase always increases). Practical implementation often requires N*2π wrapping and a large accumulator. The computation clock must be a retimed version of the reference clock. These clocks are asynchronous relative to each other, which may cause meta-stability problems. The DCO requires a frequency control code, so the phase must be converted to frequency. The TDC is an analog block, and typically has analog impairments such as mismatch; it often requires substantial area and also may draw significant current. Finally, the TDC requires analog design knowledge and is not very portable across semiconductor process generations (e.g. CMOS nodes like 65 nm, 40 nm and 32 nm).